february 2012 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch click here for this datasheet translated into chinese! fsusb42 ? low-power, two-port, hi-speed, usb2.0 (480mbps) uart switch features ? low on capacitance: 3.7pf typical ? low on resistance: 3.9 ? typical ? low power consumption: 1 a maximum - 15 a maximum i cct over an expanded voltage range (v in =1.8v, v cc =4.4v) ? wide -3db bandwidth: > 720mhz ? packaged in: - 10-lead umlp (1.4 x 1.8mm) - 10-lead msop ? 8kv esd rating, >16kv power/gnd esd rating ? over-voltage tolerance (ovt) on all usb ports up to 5.25v without external components applications ? cell phone, pda, digital camera, and notebook ? lcd monitor, tv, and set-top box important note: for additional performance information, please contact analogswitch@fairchildsemi.com . description the fsusb42 is a bi-directional, low-power, two-port, hi-speed, usb2.0 switch. configured as a double-pole, double-throw switch (dpdt) switch, it is optimized for switching between two hi-speed (480mbps) sources or a hi-speed and full-speed (12mbps) source. the fsusb42 is compatible with the requirements of usb2.0 and features an extremely low on capacitance (c on ) of 3.7pf. the wide bandwidth of this device (720mhz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. superior channel-to-channel crosstalk also minimizes interference. the fsusb42 contains special circuitry on the switch i/o pins for applications where the v cc supply is powered-off (v cc =0), which allows the device to withstand an over-voltage condition. this device is designed to minimize current consumption even when the control voltage applied to the sel pin is lower than the supply voltage (v cc ). this feature is especially valuable to ultra-portable applications, such as cell phones, allowing for direct interface with the general- purpose i/os of the bas eband processo r. other applications include switching and connector sharing in portable cell phones, pdas, digital cameras, printers, and notebook computers. ordering information part number top mark operating temperature range package fsusb42umx he -40 to +85c 10-lead, quad, ultrathin molded leadless package (umlp), 1.4 x 1.8mm fsusb42mux fsusb42 -40 to +85c 10-lead, molded small outline package (msop) jedec mo-187, 3.0mm wide micropak? is a trademark of fairchild semiconductor corporation. hsd1+ hsd2+ hsd1- hsd2- d- d+ control sel /oe figure 1. analog symbol
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 2 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch pin assignments v cc gnd 1 8 5 4 3 2 sel d+ d- hsd2+ hsd2- hsd1+ /oe 9 10 6 7 hsd1- 5 4 3 2 1 6 7 8 9 10 v cc sel d+ d- gnd /oe hsd1- hsd2- hsd1+ hsd2+ figure 2. pin assignment 10l umlp (top through view) figure 3. pin assignment 10l msop (top through view) pin definitions umlp pin# msop pin# name description 1 3 d+ usb data bus 2 4 d- usb data bus 3 5 gnd ground 4 6 hsd1- multiplexed source inputs (uart / usb) 5 7 hsd1+ multiplexed source inputs (uart / usb) 6 8 hsd2- multiplexed source inputs (usb only) 7 9 hsd2+ multiplexed source inputs (usb only) 8 10 /oe switch enable 9 1 v cc supply voltage 10 2 sel switch select truth table sel /oe function x high disconnect low low d+, d-=hsd1+, hsd1- high low d+, d-=hsd2+, hsd2-
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 3 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 5.6 v v cntrl dc input voltage (s, /oe) (1) -0.5 v cc v v sw dc switch i/o voltage (1) -0.50 5.25 v i ik dc input diode current -50 ma i out dc output current 100 ma t stg storage temperature -65 +150 c msl moisture sensitivity level (jedec j-std-020a) 1 level esd human body model, jedec: jesd22-a114 all pins 7 kv i/o to gnd 8 power to gnd 16 d+/d- 9 iec 61000-4-2 system on usb connector pins d+ & d- air discharge 15 contact 8 charged device model, jedec: jesd22-c101 2 note: 1. the input and output negative ratings may be exceeded if the input and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 4.4 v v cntrl (2) control input voltage (s, /oe) 0 v cc v v sw switch i/o voltage -0.5 4.5 v t a operating temperature -40 +85 c note: 2. the control input must be held h igh or low and it must not float.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 4 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch dc electrical char acteristics all typical value are at t a =25c unless otherwise specified. symbol parameter condition v cc (v) t a =- 40c to +85c unit min. typ. max. v ik clamp diode voltage i in =-18ma 3.0 -1.2 v v ih input voltage high 3.0 to 3.6 1.3 v 4.3 1.7 v v il input voltage low 3.0 to 3.6 0.5 v 4.3 0.7 v i in control input leakage v sw =0 to v cc 0 to 4.3 -1 1 a i oz off state leakage 0 ?? dn, hsd1n, hsd2n ?? 3.6v 4.3 -2 2 a i off power-off leakage current (all i/o ports) v sw =0v to 4.3v, v cc =0v figure 5 0 -2 2 a r on hs switch on resistance (3) v sw =0.4v, i on =-8ma figure 4, 3.0 3.9 6.5 ?? ? r on hs delta r on (4) v sw =0.4v, i on =-8ma 3.0 0.65 ? i cc quiescent supply current v cntrl =0 or v cc , i out =0 4.3 1 a i cct increase in i cc current per control voltage and v cc v cntrl =2.6v, v cc =4.3v 4.3 10 a v cntrl =1.8v, v cc =4.3v 4.3 15 a notes: 3. measured by the voltage drop between hsdn and dn pins at the indicated cu rrent through the switch. on resistance is determined by the lower of the voltage on the two (hsdn or dn ports). 4. guaranteed by characterization.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 5 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch ac electrical characteristics all typical value are for v cc =3.3v at t a =25c unless otherwise specified. symbol parameter condition v cc (v) t a =- 40c to +85c unit min. typ. max. t on turn-on time s, /oe to output r l =50 ? , c l =5pf v sw =0.8v figure 6, figure 7 3.0 to 3.6 13 30 ns t off turn-off time s, /oe to output r l =50 ? , c l =5pf v sw =0.8v figure 6, figure 7 3.0 to 3.6 12 25 ns t pd propagation delay (5) c l =5 pf, r l =50 ? figure 6, figure 8 3.3 0.25 ns t bbm break-before-make r l =50 ? , c l =5pf v sw1 =v sw2 =0.8v figure 10 3.0 to 3.6 2.0 6.5 ns o irr off isolation r l =50 ? , f=240mhz figure 12 3.0 to 3.6 -30 db xtalk non-adjacent channel crosstalk r l =50 ? , f=240mhz figure 13 3.0 to 3.6 -45 db bw -3db bandwidth r l =50 ? , c l =0pf figure 11 3.0 to 3.6 720 mhz r l =50 ? , c l =5pf figure 11 550 mhz note: 5. guaranteed by characterization. usb hi-speed-related ac electrical characteristics symbol parameter condition v cc (v) t a =- 40oc to +85oc unit min. typ. max. t sk(p) skew of opposite transitions of the same output (6) c l =5pf, r l =50 ? figure 9 3.0 to 3.6 20 ps t j total jitter (6) r l =50 ? , c l =5pf, t r =t f =500ps (10-90%) at 480mbps (prbs=2 15 ? 1) 3.0 to 3.6 200 ps note: 6. guaranteed by characterization. capacitance symbol parameter condition t a =- 40c to +85c unit min. typ. max. c in control pin input capacitance v cc =0v 1.5 pf c on d+/d- on capacitance v cc =3.3v, /oe=0v, f=240mhz figure 15 3.7 c off d1n, d2n off capacitance v cc and /oe=3.3v figure 14 2.0
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 6 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch test diagrams select hsd n dn v sel = 0 orv cc i on v on r on = v on /i on gnd v sw gnd sw select v sel = 0 orv cc nc a i dn(off) v sw gnd v v cc **each switch port is tested separately figure 4. on resistance figure 5. off leakage r l ,r s ,andc l are functions of the application environment (see ac tables for specific values) c l includes test fixture and stray capacitance. r l c l hsd n dn gnd gnd r s v sel v sw gnd v out v out t rise =2.5ns gnd v cc 90% 90% 10% 10% t fall =2.5ns v cc /2 v cc /2 input ? v /oe ,v sel output- v out 90% v oh v ol t on t off 90% v ?v v ? figure 6. ac test circuit load figure 7. turn-on / turn-off waveforms input output v oh v ol 50% 50% 50% 50% 400mv t phl t plh 0v t rise =500ps -400mv 90% 90% 10% 10% t fall = 500ps 0v output t phl +400mv t plh figure 8. propagation delay (t r t f ? 500ps) figure 9. intra-pair skew test t sk(p)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 7 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch test diagrams (continued) v cc 0.9*v out v cc /2 t bbm 0v v out input - v sel 0.9*v out t rise =2.5ns 90% 10% c l hsd n r l dn gnd gnd r s v sel v sw1 gnd v out v sw2 gnd - - r l ,r s , and c l are functions of the application environment (see ac tables for specific values) c l includes test fixture and stray capacitance. figure 10. break-before-make interval timing v out gnd gnd r t gnd gnd v s r s network analyzer v sel gnd r s and r t are functions of the application environment (see ac tables for specific values). v in r s and r t are functions of the application environment (see ac tables for specific values). v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd v sel gnd v in r t off isolation = 20 log (v out / v in ) figure 11. bandwidth figure 12. channel off isolation v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (see ac tables for specific values). v sel gnd nc v in crosstalk = 20 log (v out / v in ) figure 13. non- a djacent channel-to-channel crosstalk v sel = 0 or v cc hsd n capacitance meter s hsd n v sel = 0 or v cc hsd n capacitance meter s hsd n figure 14. channel off capacitance figure 15. channel on capacitance
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 8 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch physical dimensions a b c seating plane detail a pin#1 ident recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation is based on fsc design only. e. drawing filename: mkt-umlp10arev3. top view bottom view 0.15 c 0.08 c 0.15 c 2x 2x side view 0.10 c 0.05 3 6 1 0.10 c a b 0.05 c 0.55 max. 10 1.40 1.80 0.40 0.15 0.25 (10x) 0.35 0.45 (9x) 1.70 2.10 0.40 0.663 0.563 (9x) 0.225 (10x) 1 0.152 0.10 0.10 0.55 0.45 0.10 detail a scale : 2x 1.85 1.45 0.55 0.40 0.225 (10x) 9x 0.45 pin#1 ident optional minimial toe land pattern scale : 2x lead option 1 scale : 2x lead option 2 package edge figure 16. 10-lead, ultrathin molded leadless package (umlp) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 9 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch physical dimensions (continued) figure 17. 10-lead, molded small outline package (msop) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb42 ? rev. 1.1.5 10 fsusb42 ? low-power, two-port, hi-s peed, usb2.0 (480mbps) uart switch
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